The engineering foundation of The Theory of Embedded Intelligence — and the story of how Bill Mensch and the Western Design Center built intelligence into silicon.
What Is EIT?
Every microprocessing system can be considered an Embedded Intelligence Technology (EIT) — a deliberately engineered system for embedding intelligence into matter.
Embedded Intelligence is characterized by the ability to Sense, Process, Communicate, and Actuate (SPCA) based on information gained from understanding both itself and others, for the benefit of many. EIT is what happens when human beings figure out how to give silicon those four capabilities.
The scale is staggering. EIT runs everything from a microwave oven controller to global communications networks — and at its largest expression, EIT is now the substrate of what some have called the Global Brain, the planet-spanning information system humanity has built over the past fifty years.
EIT is also the engineering bedrock of the Theory of Embedded Intelligence (TEI). TEI proposes that intelligence is a fundamental property of the universe, expressed through SPCA at every scale. EIT is the proof of concept Bill Mensch built with his own hands. If we can engineer intelligence into silicon, then the principles by which we do it tell us something about how intelligence operates everywhere else.
The Origin of EIT
The story of EIT begins in the early 1970s with two families of microprocessing systems: the Motorola 68xx and the MOS Technology 65xx. Bill Mensch worked on both — and the 65xx architecture, which Bill helped design and which the Western Design Center (WDC) continues to develop today as the W65C02S and W65C816S, became one of the most influential microprocessor families in the history of computing.
The 65xx powered the Apple II, the Commodore 64, the Atari home computers, and the original Nintendo Entertainment System. It is the chip that put computing in the hands of an entire generation. The Intel x86 and ARM architectures eventually followed the 65xx into the marketplace for PCs and gaming systems — and many of the early generations of those systems were themselves built on top of WDC’s 65xx EIT before being replaced by later generations after enormous investment of time, energy, and capital.
But the most interesting story in this history isn’t about market share. It’s about a meeting that changed the world.
The ARM Story: A Visit to WDC, Fall 1983
In the autumn of 1983, two engineers from Cambridge, England arrived at the Western Design Center’s offices in Mesa, Arizona. Their names were Steve Furber and Sophie Wilson, and they were working for Acorn Computers — the British company building the BBC Micro, the United Kingdom’s answer to the Apple II.
They had come with a request: would Bill Mensch design a 32-bit microprocessor for them? Acorn wanted to leapfrog Apple. They wanted the British Empire’s “Beeb” to surpass the Beeb’s American competition. And they wanted Bill to build the chip that would do it.
Bill said no.
He refused to design a non-compatible 32-bit version of the W65C02S and W65C816S microprocessors. The 65xx Instruction Set Architecture was already a proven, elegant design — and Bill was not going to throw that away to chase a 32-bit fashion.
Steve Furber and Sophie Wilson returned to Cambridge determined to design their own microprocessor. They built it from scratch, using a Reduced Instruction Set Computing (RISC) approach. They called it the Acorn RISC Machine. Later it was renamed the Advanced RISC Machine. Today it is known simply as ARM.
ARM is now the most widely deployed processor architecture in the world. Nearly every mobile device powered by Apple’s iOS or Google’s Android runs on an ARM chip. The phone in your pocket is, in a real sense, the descendant of a meeting in Mesa, Arizona, where Bill Mensch said no.
Why Bill Said No: The Case for the 65xx ISA
Bill’s refusal wasn’t stubbornness. It was a principled engineering judgment about what makes an Instruction Set Architecture (ISA) effective — and that judgment has aged remarkably well.
The 65xx ISA was already proven as one of the most effective architectures in the industry, as the WDC instruction-level benchmark comparisons demonstrate. But the deeper reason has to do with how communications and computing have actually evolved over the past four decades.
Most communications today occur serially between parallel processing systems — Infrared, Bluetooth, WiFi, Ethernet. Serial communications transmit 8 bits at a time. All of the ASCII codes can be represented with 8-bit quantities. The world’s information infrastructure is fundamentally an 8-bit pipeline at its communication boundaries, no matter what’s happening inside the processors at either end.
Given that reality, it makes engineering sense to consider 8-bit architecture as the dominant design and stay with the simple elegance of the 65xx ISA. As bus speeds in modern EIT systems now exceed 1 GHz, the logical move is either to go to all serial communications even on-chip, or to drop from 32-bit fetches down to 8-bit fetches. Either path could push 65xx EIT bus speeds to 10 GHz and beyond.
This isn’t nostalgia for old chips. It’s an argument that the architectural choices made in the 1970s were closer to right than the industry realized at the time — and that the future of embedded intelligence may circle back to them.
The Hidden Power of the 65xx: Addressable Register Architecture
The 65xx EIT has one feature that is genuinely powerful but rarely recognized for what it is: its Addressable Register Architecture (ARA), which Motorola promoted under the name “memory mapped I/O.”
Calling it “memory mapped I/O” actually obscures the real innovation. Within that framing, addressable registers got lost — treated as an I/O quirk rather than a fundamental architectural advantage.
The truth is that the power of the 65xx ISA lies in its addressable register sets. On the W65C02S, these can be created in Page Zero. On the W65C816S, the same concept exists as Direct Page. Beyond that, the 65xx architecture can address 65K bytes of registers on the W65C02S and 16 megabytes of registers on the W65C816S — essentially an unlimited number of registers.
Intel took a different approach. Intel’s chips have a separate I/O instruction set, so Intel and its customers tended not to think about addressing I/O within the memory addressing space at all. As a result, an entire dimension of architectural elegance available to 65xx designers was simply absent from the x86 world.
Using advanced Direct Memory Addressing approaches, the 65xx ISA can move data around in an EIT system as fast or faster than any 32-bit or larger ISA, all while using its powerful ARA. The simplicity of the design isn’t a limitation — it’s the source of its speed and flexibility.
EIT and the Future of Embedded Intelligence
The deeper point of all this engineering history is not that one chip architecture is better than another. It’s that the way we embed intelligence into matter matters — and that the engineering decisions we make at the silicon level shape the kind of intelligence we are capable of building.
This is the bridge between EIT and TEI. The Theory of Embedded Intelligence proposes that intelligence is a fundamental property of the universe, expressed at every scale through SPCA. EIT is what happens when human beings — themselves embedded intelligences — deliberately design new substrates for that same SPCA process. Every microprocessor is, in TEI terms, a small act of intelligence creating the conditions for more intelligence.
The Western Design Center has been doing this work for over forty years. The 65xx family is still in active production, still being designed into new systems, and still being taught to new generations of engineers. The story isn’t over.
Learn More
- The Theory of Embedded Intelligence — Explore the larger framework that EIT exemplifies
- The Western Design Center — Bill Mensch’s company and the home of the 65xx family
- Bring TEI to Your AI — Use the TEI AI Master System with ChatGPT, Gemini, or Claude
- About Bill Mensch — The engineer behind EIT and the founder of TEI