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Patents By Inventor William D. Mensch, Jr.

  • U.S. Patent Number 6,052,792
    A monitor program stored in a ROM of a microcomputer chip of a computer is operated both to (1) save power by disabling all
  • U.S. Patent Number 5,737,613
    A method of operating a CMOS microcomputer to minimize power dissipation while accessing a plurality of memories including a first memory operable at a
  • U.S. Patent Number 5,511,209
    A CMOS integrated circuit microcomputer is switchable under softwarecontrol between high speed, high power operation and low speed, low power operation. The microcomputer includes
  • U.S. Patent Number 5,438,681
    The topography of an 84 lead CMOS microcomputer chip includes first,second, third, and fourth consecutive edges, with chip control logic being located along the
  • U.S. Patent Number 5,212,800
    A CMOS integrated circuit microcomputer system includes circuitry forsensing trinary logic states by using a tri-state driver circuit connected to both the input and
  • U.S. Patent Number 5,123,107
    The topography of a CMOS microcomputer chip includes first, second, third,and fourth consecutive edges, with chip control logic being located along the upper left
  • U.S. Patent Number 5,097,413
    An abort circuit for a microprocessor includes a circuit receiving andlatching an external abort signal to produce an internal abort signal, and circuitry responsive
  • U.S. Patent Number 4,876,639
    A sixteen bit microprocessor includes an emulation bit that is loaded intoan instruction register with 8 bit op codes. If the emulation bit is
  • U.S. Patent Number 4,800,487
    The topography of a CMOS microprocessor chip includes address buffercircuitry along the bottom and lower left hand edges of the chip, data bus buffers
  • U.S. Patent Number 4,739,475
    The topography of a sixteen bit CMOS microprocessor chip includingcircuitry for enabling it to emulate, under software control, a prior art 6502 microprocessor includes
  • U.S. Patent Number 4,652,992
    The topography of a CMOS microprocessor chip includes address buffercircuitry along the bottom and lower left hand edges of the chip, data bus buffers
  • U.S. Patent Number 4,263,650
    A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to
  • U.S. Patent Number 4,218,740
    A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical
  • U.S. Patent Number 4,099,232
    An interval timer in a MOS IC microprocessor system uses a countdown register of as many stages as the data bus lines (8) but
  • U.S. Patent Number 4,087,855
    A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected
  • U.S. Patent Number 4,086,627
    A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between
  • U.S. Patent Number 4,020,472
    An interface adaptor suitable for use in a microprocessor system includes an input register coupled to a bidirectional data bus of the microprocessor system.
  • U.S. Patent Number 3,991,307
    Disclosed is an integrated circuit microprocessor with a parallel binary adder whose output can be corrected on-the-fly to provide decimal results. The correction is
  • U.S. Patent Number 3,968,478
    The chip architecture of an MOS peripheral interface adaptor chip includes data bus buffers arranged along one edge of the chip, peripheral interface buffers
Disclaimer: data is provided as-is from the United States Patent and Trademark Office, modified for presentation purposes only.
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