Patents By Inventor William D. Mensch, Jr.
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- U.S. Patent Number 6,052,792
Power management and program execution location management system for CMOS microcomputer - U.S. Patent Number 5,737,613
Method of operating microcomputer to minimize power dissipation while accessing slow memory - U.S. Patent Number 5,511,209
Programmable microcomputer oscillator circuitry with synchronized fast and slow clock output signal - U.S. Patent Number 5,438,681
Topography for CMOS microcomputer - U.S. Patent Number 5,212,800
Method and apparatus for sensing trinary logic states in a microcomputer using bus holding circuits - U.S. Patent Number 5,123,107
Topography of CMOS microcomputer integrated circuit chip including core processor and memory, priority, and I/O interface circuitry coupled thereto - U.S. Patent Number 5,097,413
Abort circuitry for microprocessor - U.S. Patent Number 4,876,639
Method and circuitry for causing sixteen bit microprocessor to execute eight bit op codes to produce either internal sixteen bit operation or internal eight bit operation in accordance with an emulation bit - U.S. Patent Number 4,800,487
Topography of integrated circuit including a microprocessor - U.S. Patent Number 4,739,475
Topography for sixteen bit CMOS microprocessor with eight bit emulation and abort capability - U.S. Patent Number 4,652,992
Topography of integrated circuit CMOS microprocessor chip - U.S. Patent Number 4,263,650
Digital data processing system with interface adaptor having programmable monitorable control register therein - U.S. Patent Number 4,218,740
Interface adaptor architecture - U.S. Patent Number 4,145,751
Data direction register for interface adaptor chip - U.S. Patent Number 4,099,232
Interval timer arrangement in a microprocessor system - U.S. Patent Number 4,087,855
Valid memory address enable system for a microprocessor system - U.S. Patent Number 4,086,627
Interrupt system for microprocessor system - U.S. Patent Number 4,020,472
Master slave registers for interface adaptor - U.S. Patent Number 3,991,307
Integrated circuit microprocessor with parallel binary adder having on-the-fly correction to provide decimal results - U.S. Patent Number 3,968,478
Chip topography for MOS interface circuit - U.S. Patent Number 3,942,037
MOS edge sensing circuit - U.S. Patent Number 3,906,255
MOS current limiting output circuit
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