Philosophically speaking, before what is commonly known as the “Big Bang”, something occurred that combined energy to form the first atomic structures most likely of a hydrogen atom. “Atomic level Embedded Intelligence” will be referred to as that which informed energy to “self-assemble” to become an atomic structure. The creation of and assembly of atomic structures was seminal in that it was the beginning of matter and all that Matters to this day.
It is now believed that the EI that started it all, remains evident in all that has found a way to exist in non-life, life, and organizations of non-life and life forms.
The earliest mythological concepts and continuing on today could be considered as evolving from this first Intelligence.
The human education system is of special import in understanding EI, use, and expression in ever expanding complex system, both un-assisted and assisted by human endeavor. The continued assembly of all forms is possible through understanding. We must work together to continue the progress, constructively, in knowing and understanding that which was first experienced by that first hydrogen atom for the benefit of all that was, is, or will Be!
Philosophy of the 65xx Embedded Intelligence Technology
Philosophically speaking, any microprocessing system can be considered to be an Embedded Intelligence Technology (EIT) used for embedding intelligence in systems. From a microwave oven controller to a global form of this has been described as the “Global Brain” http://en.wikipedia.org/wiki/Global_brain for examples.
The original Motorola 68xx and MOS Technology 65xx microprocessing systems of components began in the early 1970’s. The Intel x86 technology followed the 65xx EIT into the market place for PC’s and today’s Nintendo, Sega, and Microsoft gaming systems followed the 65xx EIT as well. In fact, many of those early EIT systems were created by the WDC 65xx EIT only to be replaced by more sophisticated later generations after much investment of time, energy, and financial resources.
A particularly interesting development is associated with the ARM EIT previously known as the Acorn RISC Machine, Advanced RISC Machine and now finally just known as ARM. Most of the mobile devices supplied with Apple’s iOS and Google’s Android OS are powered by ARM EIT.
ARM’s original designers visited WDC’s offices in the Fall of 1983 in hope’s that WDC would design a 32-bit microprocessor to leap-frog Apple with the BBC’s British Empire’s equivalent of the Apple then called the Acorn or “Beeb”. When Bill refused to design a non-compatible 32-bit version of the W65C02S and W65C816S microprocessors, Steve Furber and Roger Wilson (now known as Sophia Wilson), return to Cambridge determined to design their own RISC style microprocessor. The rest is history, so to speak.
Why did Bill refuse to design a RISC microprocessor? Well the 65xx Instruction Set Architecture (ISA) was already proven as a most effective ISA and can be easily seen in these instruction level benchmark comparisons http://www.westerndesigncenter.com/wdc/AN-001_%20Instruction_Level_Performance_Comparisons.cfm .
So when evaluating an ISA one also has to consider advances in associated technology. One can easily see that most all communications occur serially between parallel processing systems, for example Infrared (IR) , Bluetooth, WiFi, and Ethernet Input/Output (IO) enabled systems.
Serial communications mostly transmit 8-bits at a time and all of the ASCII codes can be represented with 8-bit quantities. It is only natural for effective communications to consider 8-bits as the dominant architecture and stay with the simple elegance of the 65xx ISA. Now as bus speeds of EIT systems are now well above the 1 GHz, it would seem that we either go to all serial communications even on-chip or drop down from 32-bit to 8-bit fetches and stores. This could increase the bus speeds for the 65xx EIT to 10 GHz and beyond.
The one powerful feature that the 65xx EIT is well known for; however, infrequently recognized for, is its “addressable register architecture (ARA)” also known and promoted by Motorola as “memory mapped IO”. Intel has a separate IO instruction set and therefore Intel and its customers tended to take a different approach to IO interfaces and not consider addressing IO in the memory addressing space.
The problem with calling the 65xx as having “memory mapped IO” is that within that architectural concept, addressable registers became lost. The power of the 65xx ISA lies within its addressable register sets which can be created in “Page Zero” on the W65C02S also known as “Direct Page” on the W65C816S microprocessors. In addition to Page Zero addressing, the 65xx architecture can also address 65K bytes of registers and on the W65C816S 16M bytes of registers, essentially an unlimited number of registers.
Using advanced Direct Memory Addressing (DMA) approaches, the 65xx ISA can move data around in an EIT system as fast or faster than any 32-bit or beyond ISA using its powerful ARA.